As system clock speeds continue to rise, signal reliability and accuracy have become increasingly important, particularly with respect to amplitude, frequency, and distortion. Providing signals with robust duty cycles has also been desirable, as many digital circuits require a precisely controlled duty cycle for proper operation. In some cases, circuits are configured to operate on both rising and falling edges of clocks, further emphasizing the importance of maintaining a consistently accurate duty cycle for a clock signal.
Known approaches for maintaining a reliable duty cycle corrected clock signal have failed with respect to accuracy, as many systems are capable of reliably correcting a duty cycle, but only for a few specific duty cycles (e.g., 50% duty cycle). Response times and ranges of known approaches have also failed to meet increasing demands. Many implementations are unable to correct duty cycles of signals having high duty cycle variation and/or are limited by the amount a duty cycle may be adjusted.